I. Field of the Disclosure
The technology of the disclosure relates to reconfiguration of configurable co-processor cores in central processing unit (CPU)-based systems.
II. Background
A central processing unit (CPU) found in contemporary digital computers may include multiple “processor cores,” or independent processing units, for reading and executing program instructions. A multicore CPU combines two or more independent cores into a single package comprised of a single-piece integrated circuit (IC). Each core may independently implement optimizations such as superscalar execution, pipelining, and multithreading. A system with N cores is conventionally most effective when it is presented with N or more threads concurrently.
Special-purpose processors, often referred to as “hardware accelerators,” may be provided to perform certain types of operations. For example, a processor executing a program may offload certain types of operations to a hardware accelerator (e.g., a graphics accelerator or a floating-point accelerator) that is configured to efficiently perform those types of operations. Such hardware accelerators may employ specialized hardware to perform some functions faster than is possible in software running on a normal (general-purpose) CPU. The hardware accelerators may also provide improved power consumption compared to software-only execution. Hardware accelerators may be designed for computationally intensive software code. Depending upon granularity, hardware accelerators can vary from small single functional units to large blocks of multiple functional units.
Recent developments in CPU design have yielded CPUs with configurable co-processor cores that may be adaptively reconfigured to provide hardware accelerators. For example, a configurable co-processor core may be reconfigured based on a particular application that is of immediate interest to a user, and that is predicted to be executed by the CPU. The configurable co-processor core may initially be configured to provide a hardware accelerator for image processing, and then may subsequently be reconfigured to provide a hardware accelerator for collision detection for gaming. Using existing techniques, reconfiguration of a configurable co-processor core may be initiated manually, or may be initiated automatically based on simple hardware counters that track usage of specific hardware accelerators. However, automatic reconfiguration of configurable co-processor core based on simple hardware counters may not provide a sufficiently accurate model of application usage patterns. Moreover, such counter-based reconfiguration mechanisms may not provide optimal support for multitasking environments in which multiple concurrently executing applications are simultaneously contending for computing resources of the CPU.